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6.5.4.4 Ultra DMA Data Transfers Timing
Table 26 and Table 27 define the timings associated with all phases of Ultra DMA bursts.
Table 26: Ultra DMA Data Burst Timing Requirements
Name
UDMA
Mode 0
(ns)
UDMA
Mode 1
(ns)
UDMA
Mode 2
(ns)
UDMA
Mode 3
(ns)
UDMA
Mode 4
(ns)
Measurement location
(See Note 2)
Min
Max Min Max Min Max Min
Max Min Max
t 2CYCTYP
t CYC
t 2CYC
t DS
t DH
t DVS
t DVH
t CS
t CH
t CVS
t CVH
t ZFS
t DZFS
t FS
240
112
230
15.0
5.0
70.0
6.2
15.0
5.0
70.0
6.2
0
70.0
230
160
73
153
10.0
5.0
48.0
6.2
10.0
5.0
48.0
6.2
0
48.0
200
120
54
115
7.0
5.0
31.0
6.2
7.0
5.0
31.0
6.2
0
31.0
170
90
39
86
7.0
5.0
20.0
6.2
7.0
5.0
20.0
6.2
0
20.0
130
60
25
57
5.0
5.0
6.7
6.2
5.0
5.0
6.7
6.2
0
6.7
120
Sender
Note 3
Sender
Recipient
Recipient
Sender
Sender
Device
Device
Host
Host
Device
Sender
Device
t LI
0
150
0
150
0
150
0
100
0
100
Note 4
t MLI
t UI
t AZ
t ZAH
t ZAD
20
0
20
0
10
20
0
20
0
10
20
0
20
0
10
20
0
20
0
10
20
0
20
0
10
Host
Host
Note 5
Host
Device
t ENV
20
70
20
70
20
70
20
55
20
55
Host
t RFS
t RP
t IORDYZ
t ZIORDY
t ACK
t SS
160
0
20
50
75
20
125
0
20
50
70
20
100
0
20
50
60
20
100
0
20
50
60
20
100
0
20
50
60
20
Sender
Recipient
Device
Device
Host
Sender
Notes:
1.
2.
3.
4.
5.
6.
All timing measurement switching points (low to high and high to low) shall be taken at 1.5 V.
All signal transitions for a timing parameter shall be measured at the connector specified in the
measurement location column. For example, in the case of tRFS, both STROBE and – DMARDY transitions
are measured at the sender connector.
The parameter tC YC shall be measured at the recipient’s connector farthest from the sender.
The parameter tLI shall be measured at the connector of the sender or recipient that is responding to an
incoming transition from the recipient or sender respectively. Both the incoming signal and the outgoing
response shall be measured at the same connector.
The parameter tAZ shall be measured at the connector of the sender or recipient that is driving the bus
but must release the bus the allow for a bus turnaround.
See the AC Timing requirements in Table 27: Ultra DMA Data Burst Timing Descriptions.
Swissbit AG
Industriestrasse 4
Swissbit reserves the right to change products or specifications without notice.
Revision: 1.51
CH-9552 Bronschhofen
Switzerland
www.swissbit.com
industrial@swissbit.com
C-300_data_sheet_CF-HxBK_Rev151.doc
Page 31 of 99
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